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Transactions on High-Performance Embedded Architectures and Compilers II / edited by David Hutchison, Takeo Kanade, Josef Kittler, Jon M. Kleinberg, Friedemann Mattern, John C. Mitchell, Moni Naor, Oscar Nierstrasz, C. Pandu Rangan, Bernhard Steffen, Madhu Sudan, Demetri Terzopoulos, Doug Tygar, Moshe Y. Vardi, Gerhard Weikum, Per Stenström

Contributor(s): Resource type: Ressourcentyp: Buch (Online)Book (Online)Language: English Series: SpringerLink Bücher | Lecture notes in computer science ; 5470Publisher: Berlin, Heidelberg : Springer Berlin Heidelberg, 2009Description: Online-Ressource (digital)ISBN:
  • 9783642009044
Subject(s): Additional physical formats: 9783642009037 | Buchausg. u.d.T.: Transactions on high-performance embedded architectures and compilers ; 2. Berlin : Springer, 2009. XIV, 325 S.RVK: RVK: SS 4800LOC classification:
  • QA76.9.C62
DOI: DOI: 10.1007/978-3-642-00904-4Online resources: Summary: Special Section on High-Performance Embedded Architectures and Compilers -- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches -- Compiler-Assisted Memory Encryption for Embedded Processors -- Branch Predictor Warmup for Sampled Simulation through Branch History Matching -- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems -- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization -- Regular Papers -- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors -- Fetch Gating Control through Speculative Instruction Window Weighting -- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers -- Linux Kernel Compaction through Cold Code Swapping -- Complexity Effective Bypass Networks -- A Context-Parameterized Model for Static Analysis of Execution Times -- Reexecution and Selective Reuse in Checkpoint Processors -- Compiler Support for Code Size Reduction Using a Queue-Based Processor -- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC -- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.Summary: Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.PPN: PPN: 1647899346Package identifier: Produktsigel: ZDB-2-SCS | ZDB-2-LNC | ZDB-2-SEB | ZDB-2-SCS | ZDB-2-SXCS | ZDB-2-SEB
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