Testing of Interposer-Based 2.5D Integrated Circuits / by Ran Wang, Krishnendu Chakrabarty

Von:

Wang, Ran [aut]

Mitwirkende(r):

Chakrabarty, Krishnendu [oth]

Resource type: Ressourcentyp: Buch (Online)Buch (Online)Sprache: Englisch Reihen: SpringerLink Bücher | Springer eBook Collection EngineeringVerlag: Cham : Springer, 2017Beschreibung: Online-Ressource (XIV, 182 p. 118 illus., 102 illus. in color, online resource)ISBN:

9783319547145

Schlagwörter:

Andere physische Formen: 9783319547138 | Druckausg.: 978-3-319-54713-8 | Printed edition: 9783319547138 LOC-Klassifikation:

TK7888.4

DOI: DOI: 10.1007/978-3-319-54714-5Online-Ressourcen:

Zusammenfassung: This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICsZusammenfassung: Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.-PPN: PPN: 1657605736Package identifier: Produktsigel: ZDB-2-ENG

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